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| SSM4509GM N- AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement Low on-resistance Fast switching characteristic D2 D1 D2 D1 D1 D1 D2 N-CH BV DSS R DS(ON) ID G2 G2 S2 G1 S2 S1 G1 S1 30V 14m 10A -30V 20m -8.4A D1 D2 P-CH BVDSS RDS(ON) ID SO-8 Description Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM4509GM is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for applications such as low-voltage motor drives and inverters. G1 G2 S1 S2 Pb-free lead finish (second-level interconnect) Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 30 20 10 7.9 30 2.0 0.016 -55 to 150 -55 to 150 P-channel -30 20 -8.4 -6.7 -30 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit C/W 3/10/2005 Rev.1.01 www.SiliconStandard.com 1 of 8 SSM4509GM N-channel Electrical Characteristics @ T j= 25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage 2 Test Conditions VGS=0V, ID=250uA Min. 30 1 - Typ. Max. Units 0.02 14 23 6 14 14 10 36 17 430 350 14 20 3 1 25 100 65 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=10V, ID=9A VGS=4.5V, ID=5A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=9A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=20V ID=9A VDS=24V VGS=4.5V VDS=15V ID=1A RG=3.3 , VGS=10V RD=15 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1770 2830 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=1.7A, VGS=0V IS=9A, VGS=0V dI/dt=100A/s Min. - Typ. Max. Units 31 25 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 3/10/2005 Rev.1.01 www.SiliconStandard.com 2 of 8 SSM4509GM P-channel Electrical Characteristics @ Tj= 25oC (unless otherwise specified) Symbol BVDSS BV DSS/ Tj Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=70 C) o o Test Conditions VGS=0V, ID=-250uA 2 Min. -30 -1 - Typ. 0.02 14 27 4 18 16 11 40 25 Max. Units 20 30 -3 -1 -25 100 45 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA- RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss VGS=-10V, ID=-8A VGS=-4.5V, ID=-4A VDS=VGS, ID=-250uA VDS=-10V, ID=-8A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS=20V ID=-8A VDS=-24V VGS=-4.5V VDS=-15V ID=-1A RG=3.3 , VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1580 2530 540 450 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage2 Reverse Recovery Time 2 Test Conditions IS=-1.7A, VGS=0V IS=-8A, VGS=0V dI/dt=-100A/s Min. - Typ. 40 32 Max. Units -1.2 V ns nC Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135C/W when mounted on min. copper pad. 3/10/2005 Rev.1.01 www.SiliconStandard.com 3 of 8 SSM4509GM N-Channel 160 140 140 T A = 25 o C 10V 7.0V ID , Drain Current (A) 120 T A = 150 o C ID , Drain Current (A) 120 10V 7.0V 100 100 80 80 5.0V 4.5V 60 5.0V 4.5V 60 40 40 20 20 V G =3.0V 0 0 1 2 3 4 V G =3.0V 0 1 2 3 4 0 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 18 1.6 ID=5A T A =25 C 15 o 1.4 ID=9A V G =10V Normalized RDS(ON) 3 5 7 9 11 RDS(ON) (m ) 1.2 1.0 12 0.8 9 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.5 10 8 2.0 6 T j =150 o C 4 T j =25 o C VGS(th) (V) 1.2 IS(A) 1.5 2 0 1.0 0 0.2 0.4 0.6 0.8 1 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 3/10/2005 Rev.1.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 4 of 8 SSM4509GM N-Channel 14 f=1.0MHz 10000 VGS , Gate to Source Voltage (V) 12 I D =9A V DS =24V C iss 10 8 C (pF) 1000 6 4 C oss C rss 2 0 0 10 20 30 40 50 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 100us 10 Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 1ms ID (A) 10ms 1 0.1 0.1 0.05 0.02 100ms 1s 0.1 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja =135o C/W T A =25 o C Single Pulse 0.01 0.1 1 10 DC 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off)tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 3/10/2005 Rev.1.01 www.SiliconStandard.com 5 of 8 SSM4509GM P-Channel 160 120 140 T A = 25 C o -10V 100 T A = 150 C o -10V -7.0V -ID , Drain Current (A) 120 -7.0V -ID , Drain Current (A) 80 100 80 60 -5.0V -4.5V 60 -5.0V -4.5V 40 40 20 V G =-3.0V 20 V G =-3.0V 0 0 1 2 3 4 5 6 7 0 0 1 2 3 4 5 6 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 33 1.6 30 ID=-4A T A =25 C o 1.4 I D =- 8 A V G =-10V 27 Normalized R DS(ON) 1.2 RDS(ON) (m) 24 1.0 21 0.8 18 15 0.6 3 5 7 9 11 -50 0 50 100 150 -V GS ,Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.5 8 6 2 -IS(A) 4 T j =150 o C T j =25 o C -VGS(th) (V) 1.5 1 1.2 -50 2 0 0 0.2 0.4 0.6 0.8 1 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 3/10/2005 Rev.1.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 6 of 8 SSM4509GM P-Channel f=1.0MHz 14 10000 -VGS , Gate to Source Voltage (V) 12 I D =- 8 A V DS =-24V 10 C (pF) 8 C iss 1000 6 4 C oss C rss 2 0 0 10 20 30 40 50 60 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (Rthja) Duty factor=0.5 10 100us 1ms 0.2 0.1 0.1 -ID (A) 0.05 1 10ms 100ms 0.02 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135oC/W 0.1 T A =25 C Single Pulse 0.01 0.1 1 10 o 1s DC 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 3/10/2005 Rev.1.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 7 of 8 SSM4509GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 3/10/2005 Rev.1.01 www.SiliconStandard.com 8 of 8 |
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